Intel System Dma Controller Driver

When AllocateAdapterChannel transfers control to a driver's AdapterControl routine, the driver 'owns' the system DMA controller and a set of map registers. Then, the driver must set up the DMA controller for a transfer operation, as shown in the following figure.

If the driver has a StartIo routine, AllocateAdapterChannel passes a pointer to DeviceObject->CurrentIrp in the PIrp parameter to the AdapterControl routine. If, however, the driver manages its own queue of IRPs, the driver should include a pointer to the current IRP as part of the context it passes to AdapterControl.

As the previous figure shows, the driver's AdapterControl routine sets up the DMA transfer, as follows:

1. The AdapterControl routine gets the address at which to start the transfer. For the initial transfer required to satisfy an IRP, the AdapterControl routine calls MmGetMdlVirtualAddress, passing a pointer to the MDL at Irp->MdlAddress, which describes the buffer for this DMA transfer.

   MmGetMdlVirtualAddress returns a virtual address that the driver can use as an index for the system physical address where the transfer should start.

   If the IRP requires more than one transfer operation, the driver calculates an updated starting address, as described later in this section.

2. The AdapterControl routine saves the address returned by MmGetMdlVirtualAddress or calculated in step 1. This address is a required parameter (CurrentVa) to MapTransfer.

3. The AdapterControl routine calls MapTransfer to set up the system DMA controller, supplying the following parameters:

   • The adapter object pointer returned by IoGetDmaAdapter

   • A pointer (Mdl) to the MDL at Irp->MdlAddress for the current IRP

   • The MapRegisterBase handle passed to the driver's AdapterControl routine by AllocateAdapterChannel

   • The value (CurrentVa) returned by MmGetMdlVirtualAddress if this is the first call to MapTransfer for the IRP

     Otherwise, the driver supplies an updated CurrentVa value, indicating where in the buffer the next transfer operation should start.

   • A pointer to a variable (Length) indicating the number of bytes for this transfer

     If the driver can transfer all the requested data with a single call to MapTransfer and has no device-specific constraints on its DMA operations, Length can be set to the value of Length in the driver's I/O stack location of the IRP. At most, the length in bytes can be (PAGE_SIZE * the NumberOfMapRegisters returned by IoGetDmaAdapter). Otherwise, the driver must split up the request, as explained in Splitting Transfer Requests, and must update the value of Length in subsequent calls to MapTransfer for the current IRP.

   • A Boolean value (WriteToDevice), indicating the direction of the transfer operation (TRUE to transfer data from system memory to the device)

   MapTransfer returns a logical address. Drivers that use system DMA must ignore this value.

4. The AdapterControl routine sets up the device for the DMA operation.

5. The AdapterControl routine returns KeepObject.

Setting Up the System DMA Controller for Packet-Based DMA.; 3 minutes to read; t; D; T; In this article. When AllocateAdapterChannel transfers control to a driver's AdapterControl routine, the driver 'owns' the system DMA controller and a set of map registers. Then, the driver must set up the DMA controller for a transfer operation, as shown in the following figure. In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using BR (Bus Request) and BG signals, which are the two signals controlling the interface between the CPU and the DMA controller. However, in cycle stealing mode, after one byte of data transfer, the control of the system bus is. Install Intel Serial IO DMA Controller driver for Windows 10 x64, or download DriverPack Solution software for automatic driver installation and update. 2) Use the host DMA engine. Host DMA specs are as follows: System peripheral: Intel Corporation Sky Lake-E CBDMA Registers (rev 07) Subsystem: Intel Corporation Sky Lake-E CBDMA Registers Kernel driver in use: ioatdma Kernel modules: ioatdma. There are 16 such registers(8 per NUMA) and while checking the DMA channels, we can see 16. DMA Reference Design Block Diagram The reference design uses an external memory connected to the Intel® memory controller that can access up to 128 MB of on-board external memory. The read DMA moves the data from the system memory to the external memory. The write DMA moves the data from the external memory to the system memory.

When the device indicates that its current DMA operation has completed, the driver should call FlushAdapterBuffers, usually from the driver's DpcForIsr routine.

The DpcForIsr routine or another driver routine that completes a DMA operation calls FlushAdapterBuffers to ensure that any data cached in the system DMA controller is read into system memory or written out to the device. The same routine also must call MapTransfer again if it is necessary to reprogram the system DMA controller to transfer more data for the current IRP. Similarly, it must call FlushAdapterBuffers again following each transfer operation.

If a driver must call MapTransfer more than once for the current IRP, it supplies the same adapter object pointer, Mdl pointer, MapRegisterBase handle, and transfer direction in every call. However, the driver must update the CurrentVa and Length parameters before it makes the second and any subsequent calls to MapTransfer. To calculate an updated value for each of these parameters, use the following formulas:

• CurrentVa = CurrentVa + (Length requested in the preceding call to MapTransfer)

• Length = Minimum (remaining Length to be transferred, (PAGE_SIZE * NumberOfMapRegisters returned by IoGetDmaAdapter))

The context information each driver should maintain about its DMA transfers depends on the needs of its particular device. Typical context might include the current virtual address in the MDL (CurrentVa), the number of bytes transferred so far, the number of bytes remaining to transfer, possibly a pointer to the current IRP, and any other information the driver writer deems useful.

When the requested transfer is complete, or if the driver must return an error status for the IRP, the driver should call FreeAdapterChannel promptly to release the system DMA controller for other drivers and this driver to use.

Intel 8237 is a direct memory access (DMA) controller, a part of the MCS 85 microprocessor family. It enables data transfer between memory and the I/O with reduced load on the system's main processor by providing the memory with control signals and memory address information during the DMA transfer.

The 8237 is a four-channel device that can be expanded to include any number of DMA channel inputs. The 8237 is capable of DMA transfers at rates of up to 1.6 megabyte per second. Each channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k bytes with a single programming.^[1]

A single 8237 was used as the DMA controller in the original IBM PC and IBM XT. The IBM PC AT added another 8237 in master-slave configuration, increasing the number of DMA channels from four to seven.^[2] Later IBM-compatible personal computers may have chip sets that emulate the functions of the 8237 for backward compatibility.

Modes[edit]

The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used:

• Single - One DMA cycle, one CPU cycle interleaved until address counter reaches zero.^[3]
• Block - Transfer progresses until the word count reaches zero or the EOP signal goes active.^[3]
• Demand - Transfers continue until TC or EOP goes active or DRQ goes inactive. The CPU is permitted to use the bus when no transfer is requested.^[3]
• Cascade - Used to cascade additional DMA controllers. DREQ and DACK is matched with HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals is executed by cascaded chip.^[3]

Memory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.^[3]

In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It is used to repeat the last transfer.^[3]

The terminal count (TC) signals end of transfer to ISA cards. At the end of transfer an auto initialize will occur configured to do so.

Single mode[edit]

In single mode only one byte is transferred per request. For every transfer, the counting register is decremented and address is incremented or decremented depending on programming. When the counting register reaches zero, the terminal count TC signal is sent to the card.^[4][5]

The DMA request DREQ must be raised by the card and held active until it is acknowledged by the DMA acknowledge DACK.^[4]

Block transfer mode[edit]

The transfer is activated by the DREQ which can be deactivated once acknowledged by DACK. The transfer continues until end of process EOP (either internal or external) is activated which will trigger terminal count TC to the card. Auto-initialization may be programmed in this mode.^[4]

Demand transfer mode[edit]

The transfer is activated by DREQ and acknowledged by DACK and continues until either TC, external EOP or DREQ goes inactive. Only TC or external EOP may activate auto-initialization if this is programmed.^[4]

Internal registers[edit]

The internal registers used in the 8237 for data transfer are as follows:

• Base address register: To store the initial address from where data transfer will take place
• Base word count register: To store the number of transfers to be performed
• Current address register: To store the current address from where data is being transferred
• Current word count register: To store the number of transfers remaining to be performed
• Temporary address register: To hold address of data during memory-to-memory transfer
• Temporary word count register: To hold number of transfers to be performed in memory-to-memory transfer
• Mode register: 8-bit register which stores the channel to be used, the operating mode, i.e. the transfer mode, and other transfer parameters
• Command register: 8-bit register which initializes the channel to be used for data transfer
• Request register: 8-bit register used to indicate which channel is requesting for data transfer
• Mask register: 8-bit register used to mask a particular channel from requesting for DMA service
• Status register: 8-bit register used to indicate which channel is currently under DMA service and some other parameters

IBM PC use[edit]

As a member of the Intel MCS-85 device family, the 8237 is an 8-bit device with 16-bit addressing. However, it is compatible with the 8086/88 microprocessors. The IBM PC and PC XT models (machine types 5150 and 5160) have an 8088 CPU and an 8-bit system bus architecture; the latter interfaces directly to the 8237, but the 8088 has a 20-bit address bus, so four additional 4-bit address latches, one for each DMA channel, are added alongside the 8237 to augment the address counters. However, because these external latches are separate from the 8237 address counters, they are never automatically incremented or decremented during DMA operations, making it impossible to perform a DMA operation across a 64 KiB address boundary. Attempts to cross a 64 KiB boundary in a DMA transfer will wrap around within one 64 KiB block of memory. (For example, if a DMA channel and the associated address latch were programmed to transfer 256 bytes to ascending addresses starting at address 0x3FF8C, instead of transferring to addresses 0x3FF8C through 0x4008B, data would be transferred to addresses 0x3FF8C through 0x3FFFF and then to 0x30000 through 0x3008B.)

The IBM PC AT (machine type 5170) and 100% compatibles use an 80286 CPU and a 16-bit system bus architecture. In addition to the 8237 from the PC and XT models, a second, cascaded 8237 is added, for 16-bit DMA transfers. This is possible, despite the 8237 being an 8-bit device, because the 8237 performs transfers between an I/O port and memory as 'fly-by' transfers in which the data is placed onto the bus by the source memory or I/O port and directly read at the same time by the destination I/O port or memory, without being handled by the 8237. For this mode of transfer, the width of the data bus is essentially immaterial to the 8237 (as long as it is connected to a data bus at least 8 bits wide, for programming the 8237 registers). The second 8237 in an AT-class PC provides three 16-bit DMA channels (its channels 1 through 3, named channels 5 through 7 in the PC AT); its channel 0 (named channel 4 in the PC AT) is used in cascade mode to connect the 8237 for 8-bit DMA as the 'slave' in the cascade arrangement; the 8237 providing the 16-bit channels is the 'master'. So that it can address 16-bit words, it is connected to the address bus in such a way that it counts even addresses (0, 2, 4, ...) instead of single addresses. Like the first 8237, it is augmented with four address-extension registers. In an AT-class PC, all eight of the address augmentation registers are 8 bits wide, so that full 24-bit addresses—the size of the 80286 address bus—can be specified. DMA transfers on any channel still cannot cross a 64 KiB boundary. (16-bit DMA is limited to 32,768 16-bit words, even though a DMA channel can count through 65536 addresses; the most-significant bit of the address counter from a 16-bit DMA channel is ignored.) Because the 8237 memory-to-memory DMA mode operates by transferring a byte from the source memory location to an internal temporary 8-bit register in the 8237 and then from the temporary register to the destination memory location, this mode could not be used for 16-bit memory-to-memory DMA, as the temporary register is not large enough. Additionally, memory-to-memory 16-bit DMA would require use of channel 4, conflicting with its use to cascade the 8237 that handles the 8-bit DMA channels. However, on the AT, 8-bit DMA channel 0 is no longer used for DRAM refresh, having been replaced by specialized refresh logic, so it should be possible to perform 8-bit memory-to-memory DMA using channels 0 and 1 without interrupting DRAM refresh.

The design of 8237-based DMA in PC AT compatibles was not updated with the move to the 32-bit CPUs and 32-bit system bus architectures. Consequently, a limitation on these machines is that the 8237 DMA controllers with their companion address 'page' extension registers only can address 16 MiB of memory, according to the original design oriented around the 80286 CPU, which itself has this same addressing limitation.^[6] This means that for other memory areas, the data has to be transferred first by DMA from the I/O device to an intermediate buffer in the first 16 MiB of the physical address space, and then moved to the final memory by the CPU; or, in the other direction, it must be transferred from the initial memory to the intermediate buffer by the CPU before being transferred by DMA from that buffer to the I/O device. This technique is called 'bounce buffer'. In general, it loses any overall speed benefit associated with DMA, but it may be necessary if a peripheral requires to be accessed by DMA due to either demanding timing requirements or hardware interface inflexibility.

In the PS/2 series of computers, IBM did update the DMA hardware to support 32-bit data and addresses in some systems with 80386 CPUs, but they did this by replacing the 8237 with a new DMA controller design. The new design includes an 8237 compatibility mode for downward compatibility with the PC AT.

Intel Controller Downloads

Integration into chipsets[edit]

Although this device may not appear as a discrete component in modern personal computer systems, it does appear within system controller chip sets. For example, the PIIX integrated two 8237 controllers for ISA bus DMA.^[7][8]

Variants[edit]

1. ^megabytes per second in 64KB block
2. ^In quantities of 100 and up

See also[edit]

• Intel 8284 - Clock generator
• Intel 8288 - Bus controller
• 8250 UART - Asynchronous serial controller (EIA-232)
• Intel 8253 - Programmable Interval Timer (PIT)
• Intel 8255 - Programmable Peripheral Interface (PPI)
• Intel 8259 - Programmable Interrupt Controller (PIC)
• Parallel ATA (P-ATA)
• Industry Standard Architecture (ISA)
• Input/output base address on IBM PC compatibles

References[edit]

1. ^Intel microprocessors by Barry B Brey
2. ^N. MATHIVANAN (2007). PC-BASED INSTRUMENTATION: CONCEPTS AND PRACTICE. PHI Learning Pvt. Ltd. pp. 227–229. ISBN978-81-203-3076-4.
3. ^ ^abcdefaluzina.org - Intel 8237/8237-2 High performance. Programmable DMA controller (.pdf) datasheet
4. ^ ^abcdbooks.google.com - Advanced Microprocessors And Peripherals, 2006 p312/313
5. ^pinouts.ru - ISA bus pinout and wiring, 2008-10-20
6. ^brokenthorn.com - Operating Systems Development Series
7. ^https://pdos.csail.mit.edu/6.828/2012/readings/hardware/8237A.pdf
8. ^http://pdf.datasheetcatalog.com/datasheet/Intel/mXvqwzr.pdf
9. ^Intel Corporation, 'Microcomputer Components: New Intel 8237 DMA Controller provides a 5 MHz DMA answer for 8088 and 8085A-2 based systems', Intel Preview, May/June 1979, Pg 9.

External links[edit]

• DMA: What it is and How it Works FreeBSD Developers' Handbook. 1997 (internet archive).

The 8237 is a four-channel device that can be expanded to include any number of DMA channel inputs. The 8237 is capable of DMA transfers at rates of up to 1.6 megabyte per second. Each channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k bytes with a single programming.^[1]

A single 8237 was used as the DMA controller in the original IBM PC and IBM XT. The IBM PC AT added another 8237 in master-slave configuration, increasing the number of DMA channels from four to seven.^[2] Later IBM-compatible personal computers may have chip sets that emulate the functions of the 8237 for backward compatibility.

Modes[edit]

The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used:

• Single - One DMA cycle, one CPU cycle interleaved until address counter reaches zero.^[3]
• Block - Transfer progresses until the word count reaches zero or the EOP signal goes active.^[3]
• Demand - Transfers continue until TC or EOP goes active or DRQ goes inactive. The CPU is permitted to use the bus when no transfer is requested.^[3]
• Cascade - Used to cascade additional DMA controllers. DREQ and DACK is matched with HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals is executed by cascaded chip.^[3]

Memory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.^[3]

In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It is used to repeat the last transfer.^[3]

The terminal count (TC) signals end of transfer to ISA cards. At the end of transfer an auto initialize will occur configured to do so.

Single mode[edit]

In single mode only one byte is transferred per request. For every transfer, the counting register is decremented and address is incremented or decremented depending on programming. When the counting register reaches zero, the terminal count TC signal is sent to the card.^[4][5]

The DMA request DREQ must be raised by the card and held active until it is acknowledged by the DMA acknowledge DACK.^[4]

Block transfer mode[edit]

The transfer is activated by the DREQ which can be deactivated once acknowledged by DACK. The transfer continues until end of process EOP (either internal or external) is activated which will trigger terminal count TC to the card. Auto-initialization may be programmed in this mode.^[4]

Demand transfer mode[edit]

The transfer is activated by DREQ and acknowledged by DACK and continues until either TC, external EOP or DREQ goes inactive. Only TC or external EOP may activate auto-initialization if this is programmed.^[4]

Internal registers[edit]

The internal registers used in the 8237 for data transfer are as follows:

• Base address register: To store the initial address from where data transfer will take place
• Base word count register: To store the number of transfers to be performed
• Current address register: To store the current address from where data is being transferred
• Current word count register: To store the number of transfers remaining to be performed
• Temporary address register: To hold address of data during memory-to-memory transfer
• Temporary word count register: To hold number of transfers to be performed in memory-to-memory transfer
• Mode register: 8-bit register which stores the channel to be used, the operating mode, i.e. the transfer mode, and other transfer parameters
• Command register: 8-bit register which initializes the channel to be used for data transfer
• Request register: 8-bit register used to indicate which channel is requesting for data transfer
• Mask register: 8-bit register used to mask a particular channel from requesting for DMA service
• Status register: 8-bit register used to indicate which channel is currently under DMA service and some other parameters

IBM PC use[edit]

As a member of the Intel MCS-85 device family, the 8237 is an 8-bit device with 16-bit addressing. However, it is compatible with the 8086/88 microprocessors. The IBM PC and PC XT models (machine types 5150 and 5160) have an 8088 CPU and an 8-bit system bus architecture; the latter interfaces directly to the 8237, but the 8088 has a 20-bit address bus, so four additional 4-bit address latches, one for each DMA channel, are added alongside the 8237 to augment the address counters. However, because these external latches are separate from the 8237 address counters, they are never automatically incremented or decremented during DMA operations, making it impossible to perform a DMA operation across a 64 KiB address boundary. Attempts to cross a 64 KiB boundary in a DMA transfer will wrap around within one 64 KiB block of memory. (For example, if a DMA channel and the associated address latch were programmed to transfer 256 bytes to ascending addresses starting at address 0x3FF8C, instead of transferring to addresses 0x3FF8C through 0x4008B, data would be transferred to addresses 0x3FF8C through 0x3FFFF and then to 0x30000 through 0x3008B.)

The IBM PC AT (machine type 5170) and 100% compatibles use an 80286 CPU and a 16-bit system bus architecture. In addition to the 8237 from the PC and XT models, a second, cascaded 8237 is added, for 16-bit DMA transfers. This is possible, despite the 8237 being an 8-bit device, because the 8237 performs transfers between an I/O port and memory as 'fly-by' transfers in which the data is placed onto the bus by the source memory or I/O port and directly read at the same time by the destination I/O port or memory, without being handled by the 8237. For this mode of transfer, the width of the data bus is essentially immaterial to the 8237 (as long as it is connected to a data bus at least 8 bits wide, for programming the 8237 registers). The second 8237 in an AT-class PC provides three 16-bit DMA channels (its channels 1 through 3, named channels 5 through 7 in the PC AT); its channel 0 (named channel 4 in the PC AT) is used in cascade mode to connect the 8237 for 8-bit DMA as the 'slave' in the cascade arrangement; the 8237 providing the 16-bit channels is the 'master'. So that it can address 16-bit words, it is connected to the address bus in such a way that it counts even addresses (0, 2, 4, ...) instead of single addresses. Like the first 8237, it is augmented with four address-extension registers. In an AT-class PC, all eight of the address augmentation registers are 8 bits wide, so that full 24-bit addresses—the size of the 80286 address bus—can be specified. DMA transfers on any channel still cannot cross a 64 KiB boundary. (16-bit DMA is limited to 32,768 16-bit words, even though a DMA channel can count through 65536 addresses; the most-significant bit of the address counter from a 16-bit DMA channel is ignored.) Because the 8237 memory-to-memory DMA mode operates by transferring a byte from the source memory location to an internal temporary 8-bit register in the 8237 and then from the temporary register to the destination memory location, this mode could not be used for 16-bit memory-to-memory DMA, as the temporary register is not large enough. Additionally, memory-to-memory 16-bit DMA would require use of channel 4, conflicting with its use to cascade the 8237 that handles the 8-bit DMA channels. However, on the AT, 8-bit DMA channel 0 is no longer used for DRAM refresh, having been replaced by specialized refresh logic, so it should be possible to perform 8-bit memory-to-memory DMA using channels 0 and 1 without interrupting DRAM refresh.

The design of 8237-based DMA in PC AT compatibles was not updated with the move to the 32-bit CPUs and 32-bit system bus architectures. Consequently, a limitation on these machines is that the 8237 DMA controllers with their companion address 'page' extension registers only can address 16 MiB of memory, according to the original design oriented around the 80286 CPU, which itself has this same addressing limitation.^[6] This means that for other memory areas, the data has to be transferred first by DMA from the I/O device to an intermediate buffer in the first 16 MiB of the physical address space, and then moved to the final memory by the CPU; or, in the other direction, it must be transferred from the initial memory to the intermediate buffer by the CPU before being transferred by DMA from that buffer to the I/O device. This technique is called 'bounce buffer'. In general, it loses any overall speed benefit associated with DMA, but it may be necessary if a peripheral requires to be accessed by DMA due to either demanding timing requirements or hardware interface inflexibility.

In the PS/2 series of computers, IBM did update the DMA hardware to support 32-bit data and addresses in some systems with 80386 CPUs, but they did this by replacing the 8237 with a new DMA controller design. The new design includes an 8237 compatibility mode for downward compatibility with the PC AT.

Intel Controller Downloads

Integration into chipsets[edit]

Although this device may not appear as a discrete component in modern personal computer systems, it does appear within system controller chip sets. For example, the PIIX integrated two 8237 controllers for ISA bus DMA.^[7][8]

Variants[edit]

1. ^megabytes per second in 64KB block
2. ^In quantities of 100 and up

See also[edit]

• Intel 8284 - Clock generator
• Intel 8288 - Bus controller
• 8250 UART - Asynchronous serial controller (EIA-232)
• Intel 8253 - Programmable Interval Timer (PIT)
• Intel 8255 - Programmable Peripheral Interface (PPI)
• Intel 8259 - Programmable Interrupt Controller (PIC)
• Parallel ATA (P-ATA)
• Industry Standard Architecture (ISA)
• Input/output base address on IBM PC compatibles

References[edit]

1. ^Intel microprocessors by Barry B Brey
2. ^N. MATHIVANAN (2007). PC-BASED INSTRUMENTATION: CONCEPTS AND PRACTICE. PHI Learning Pvt. Ltd. pp. 227–229. ISBN978-81-203-3076-4.
3. ^ ^abcdefaluzina.org - Intel 8237/8237-2 High performance. Programmable DMA controller (.pdf) datasheet
4. ^ ^abcdbooks.google.com - Advanced Microprocessors And Peripherals, 2006 p312/313
5. ^pinouts.ru - ISA bus pinout and wiring, 2008-10-20
6. ^brokenthorn.com - Operating Systems Development Series
7. ^https://pdos.csail.mit.edu/6.828/2012/readings/hardware/8237A.pdf
8. ^http://pdf.datasheetcatalog.com/datasheet/Intel/mXvqwzr.pdf
9. ^Intel Corporation, 'Microcomputer Components: New Intel 8237 DMA Controller provides a 5 MHz DMA answer for 8088 and 8085A-2 based systems', Intel Preview, May/June 1979, Pg 9.

External links[edit]

• DMA: What it is and How it Works FreeBSD Developers' Handbook. 1997 (internet archive).

Intel System Dma Controller Driver Updater